
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
12 of 16
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
tWC
t
WR1
t
DS
t
AS
t
WEZ
t
DH1
DATA INPUT
DQ0-DQ7
WE
CE
A0-A16
DATA OUTPUT
t
WEW
VALID
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
t
WC
t
WR2
tDS
tDH2
t
AS
DATA INPUT
WE
CE
A0-A16
t
CEW
VALID
DQ0-DQ7